The present invention concerns an apparatus and method which provides a circuit reset to an electronic device without the addition of a dedicated I/0 pin.
When powering up an electronic device, such as a very large scale integrated (VLSI) circuit, it is desirable to have the electronic device in a known state. For this reason reset circuitry is typically added to the electronic device.
For example, often an input/output (I/0) pin of the electronic device is dedicated to be used as a reset pin. This reset pin is connected, for example, to the active-low reset inputs of flip-flops within the electronic device. During initial power-up, the reset input is held at logic 0 This causes the flip-flops in the electronic device to be held in their reset state. Once the electronic device has been fully powered up, the reset pin is placed at logic 1, allowing the electronic device to operate.
However, electronic devices are limited in the number of I/0 pins which may be included. Often times there is no available I/0 pin which may be dedicated to use as a reset pin. In cases such as this, a power-on-reset circuit may be utilized.
A power-on-reset circuit detects when the electronic device on which the power-on-reset circuit resides is powered up. Once the power-on-reset circuit detects power up of the electronic device, the power-on-reset circuit holds its output at logic 0 for a period of time sufficient for the entire electronic device to receive full power-up. While the power-on-reset circuit holds its output at logic 0, the electronic device performs a reset. After the entire electronic device has received full power up, the power-on-reset raises its output to logic 1. When the power-on-reset raises its output to logic 1, the reset sequence is completed.
Power-on-reset circuits have several disadvantages. For example, the length of time after power-up that a power-on-reset circuit holds it output at logic 0 varies depending on processing factors, operating temperature and power supply voltages. Also, the reset may only be initiated when the electronic device is powered down. Additionally, a user has no control over the timing of the reset cycle.
Further, electronic devices are typically tested using automatic test equipment (ATE). Often times it is desirable for an ATE to loop through a number of test vectors, each of the test vectors beginning with a reset of the electronic device. Such vector looping is an important debugging and characterization procedure which is performed with power constantly applied to the electronic device under test. Unfortunately, use of a conventional power-on-reset circuit does not allow such vector looping because an electronic device including a conventional power-on-reset circuit does not issue a reset without the removing and then re-applying of power to the electronic device.